application note AN30 AN30-1 interfacing the x24c44/45 novrams to the motorola 6805 microcontroller using the spi port by applications staff, march 1991 the following code demonstrates how the xicor x24c44/45 serial novrams could be interfaced to the 6805 microcont r oller family when connected as shown in figure 1. the interface uses the spi port, with the miso pin connected to do, mosi connected to di, and sck connected to sk. ce is generated from another port pin. additional code can be found on the xicor web site at http://www.xicor.com that will implement inter- faces between the 6805 microcontroller family and other xicor serial devices. vcc vcc u2 6805 vpp 8 vstby 7 ex 6 xt 5 reset 2 int1 3 pa0 33 pa1 34 pa2 35 pa3 36 pa4 37 pa5 38 pa6 39 pa7 40 pb0 25 pb1 26 pb2 27 pb3 28 pb4 29 pb5 30 pb6 31 pb7 32 pc0 9 pc1 10 pc2 11 pc3 12 pc4 13 pc5 14 pc6 15 pc7 16 pd0 24 pd1 23 pd2 22 pd3 21 pd4 20 pd5 19 pd6 18 pd7 17 u1 x24c44 di 3 ce 1 sk 2 recall 6 store 7 do 4 fi g ure 1. t y pical hardware connection for interfacin g an x24c44 to 6805 microcontrollers
xicor application note AN30-2 AN30 **************************************************************************** * this code was designed to demonstrate how the x24c44 could be interfaced * * to the 68hc05 microcontroller. the interface uses the serial spi port to * * communicate with the x24c44. the 68hc05 is configured as a master and * * the x24c44 is the slave. the x24c44 ce signal is generated with a port * * line. the spi port provides an interface that greatly minimizes the * * software required to communicate with the x24c44. * * * * the code shown demonstrates rcl, wren, read, write, and store * * instructions. the remaining instructions (wrds and for the x24c45, enas) * * can be issued using the routine as other non-data instructions. * * * * the program issues a sequence of instructions to read the contents of * * address 5 and stores the same value in address 9. the sequence of * * instructions is as follows: * * * * 1) rcl sets the previous recall latch * * 2) wren sets the write enable latch * * 3) read data from address 5 is read * * 4) write the data read during step 3 is written to address 9 * * 5) sto the ram's contents are transferred to the eeprom * * * * data transfer is performed with the most significant bit first. * **************************************************************************** cebit equ 2 bit number indicating port d ce position spif equ 7 bit indicating end of transmission ddra equ $04 port a data direction register address porta equ $00 port a address wrds equ $80 reset write enable latch sto equ $81 transfer data from ram to eeprom enas equ $82 enable autostore (x24c45) write equ $83 ram write wren equ $84 set write enable latch rcl equ $85 transfer data from eeprom to ram and does wrds read equ $86 ram read spcr equ $0a spi control register spsr equ $0b spi status register spdr equ $0c pi data register addr equ $80 location for x24c44 address to access inst equ $81 instruction for part rwdat equ $82 location for x24c44 data transferred **************************************** * reset vector to beginning of program * **************************************** org $ffe reset vector to program entry point fdb $0100 ****************************** * start of program execution * ****************************** org $0100 beginning of executable code begin: lda #$04 sta ddra bclr #cebit,porta bring ce low lda #$50 initialize spi port sta spcr lda spsr make sure spi spif bit is reset lda #rcl perform a recall to set the sta inst recall latch jsr cehigh jsr outbyt jsr celow
AN30-3 xicor application note AN30 lda #wren perform a write enable to set sta inst the write enable latch jsr cehigh jsr outbyt jsr celow lda #$05 read the contents of address 5 sta addr the value read will be stored jsr rdwrd in rwdata lda #$09 write the data just read into sta addr address 9 jsr wrwrd perform a store operation lda #sto sta inst jsr cehigh jsr outbyt jsr celow bra * loop until reset **************************************************************** * write the word specified in rwdat. the address to be written * * is specified in addr. * **************************************************************** wrwrd: jsr cehigh write value in rwdat into location lda addr justify address lsla lsla lsla ora #write mask in write instruction jsr outbyt send write instruction lda rwdat jsr outbyt send first byte of data lda rwdat+1 jsr outbyt send second byte of data jsr celow rts ************************************************************* * read the word at the location specified in addr. the data * * read will be placed in rwdat. * ************************************************************* rdwrd: jsr cehigh read the address specified in addr lda addr justify address lsla lsla lsla ora #read mask in read instruction jsr outbyt send read instruction jsr outbyt 'read' first byte sta rwdat save first byte sent back from x24c44 jsr outbyt 'read' second byte sta rwdat+1 save second byte sent back from x24c44 jsr celow rts *********************************************************************** * send a byte out to the x24c44 and read what is sent back on the do * * pin. data is shifted out to the x24c44 on the mosi pin. while the * * shifting is taking place the level from the x24c44 do pin is being * * read by the miso input. clocking for the x24c44 is generated by the * * spi sck output. the full duplex method of data transfer means that * * the same routine that is used to write to the x24c44 can be used * * for the read operation. the routine waits until the transfer is * * completed by polling the spif bit in the spi control register. once * * the transfer has completed the data sent back from the x24c44 is *
xicor application note AN30-4 AN30 * read from the spdr. * *********************************************************************** outbyt:sta spdr send byte out wait2: brclr #spif,spsr,wait2 wait for transfer lda spdr read byte sent back rts ***************** * bring ce high * ***************** cehigh:bset #cebit,porta bring ce high rts **************** * bring ce low * **************** celow: bclr #cebit,porta bring ce low rts
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